Ajay Kolupula

Ajay Kolupula is a Design Verification Engineer currently working at AMD since September 2023, focusing on the verification of Ethernet IP systems, including TSN systems and Time Aware DMA. Previously, Ajay held the position of Verification Engineer - 1 at SmartSoC Solutions Pvt Ltd since August 2022, where responsibilities included the verification of a 100G Ethernet Bridge at various levels and implementing monitors and scoreboards. Ajay began the professional journey as an RTL Design and Verification Trainee, contributing to the 100G Ethernet Bridge project and developing initialization sequences and configuration sequences. Prior to that, Ajay was an RTL Design and Verification Trainee at AARK IC Technologies, where an APB master environment was implemented and verified. Experience also includes working as a Field Service Engineer at ECIL-Rapiscan Limited. Ajay holds a Bachelor of Technology in Electronics and Communication Engineering from JNTUH College of Engineering Hyderabad and a Diploma of Education in Electronics and Communication Engineering from Brilliant College of Education.