Jose C.

Jose C. is a seasoned professional in electrical engineering with extensive experience in the semiconductor industry. With a background that includes roles such as PMTS and Director of DFT/DFD and Post-Silicon Validation at AMD, and Senior Verification Lead at Alphawave IP Inc., Jose has demonstrated expertise in design and validation. Previous positions at AMD include Senior Manager ASIC/Layout Design Engineer, SOC Design Staff Engineer, and DFT IP Architect. Early career experience at Intel involved roles as an Array DFT Design and Cache Validation Engineer, and DFT Verification Engineer. Jose holds a Bachelor of Science degree in Electrical Engineering from Universidad de Costa Rica, earned between 2000 and 2003.