Saral Aggarwal

Saral Aggarwal is a Staff Design Engineer at AMD since September 2021, previously serving as a Senior Design Engineer and Low Power Design and Verification Engineer at Qualcomm from February 2017 to September 2021, with an earlier role as a Digital Design Intern at Qualcomm in 2016. Saral's experience includes working with server SOC front end design, executing implementation flows like PLDRC and CDC, and gaining hands-on experience in RTL design with Verilog and formal verification using System Verilog Assertions. Saral also interned at Texas Instruments between June 2014 and June 2015. Educational qualifications include a Master’s Degree in VLSI from the University of Michigan (2015-2016) and a Bachelor’s Degree in Instrumentation and Control Engineering from Netaji Subhas Institute of Technology (2011-2015).