Navod Jayawardhane

Navod Jayawardhane is currently a Teaching Assistant at Carnegie Mellon University, supporting courses in Logic Design and Verification as well as the Structure and Design of Digital Systems. With experience managing FPGA/SystemVerilog projects and teaching various lab sessions, Navod has actively engaged with undergraduate students. Previous roles include Hardware Engineering Intern at IMC Trading and SoC Design Intern at Apple, where skills in circuit design and automation were further developed. As the System Lead and Captain of the Grounded Low Voltage team at Carnegie Mellon Racing, Navod oversaw the electronic systems for an electric-powered racing car and contributed to innovative projects such as Data Acquisition systems and Hardware-In-The-Loop platforms. Navod holds a Bachelor of Science in Electrical and Computer Engineering and is pursuing a Master of Science in the same field at Carnegie Mellon University.