Jorge Virgilio de Almeida

Jorge Virgilio de Almeida is an experienced Analog Engineer currently working at Ciena since October 2024. Prior to this role, Jorge held various positions at LATYS, including RF Lead and RF/Antenna Designer, from May 2023 to September 2024. Jorge's research experience includes a self-powered base station project for 5G-IoT applications during a research internship at SBB structures and work on metamaterial-based inductive power transmission systems at CETUC. Additional research internships focused on metamaterial-inspired lenses and algorithms for assisted GPS localization. Jorge also gained practical training in electrical locomotive maintenance at SNCF and technical experience in communication lab maintenance. Jorge's academic background includes a Ph.D. in Electrical Engineering from Polytechnique Montréal, an M.Sc. from Pontifícia Universidade Católica do Rio de Janeiro, and a Generalist Engineer degree from Centrale Lyon, along with a Bachelor of Engineering in Electrical Engineering from Pontifícia Universidade Católica do Rio de Janeiro.