VP

Vedesh Pothugunta

ASIC Design Verification Engineer at Cisco

Vedesh Pothugunta is an experienced ASIC Design Verification Engineer with a strong background in pre-silicon verification and system-on-chip design. Professional experience includes internships at AMD and Intel Corporation, contributing to Infinity Fabric pre-silicon verification and pre-silicon SoC verification. Before these roles, Vedesh worked as a Viterbi Information and Instructional Technology Student Worker at USC Viterbi School of Engineering. Vedesh holds a Master's degree in Computer Engineering from the University of Southern California, obtained in May 2023, and a Bachelor's degree in Electronics and Communications Engineering from Vellore Institute of Technology, completed in 2018.

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