Paresh Upadhyay

Paresh Upadhyay is a highly experienced technical professional currently serving as a Member of Technical Staff at Expedera Inc. since May 2023, focusing on scalable neural engine semiconductor IP and AI inference applications. Prior experience includes significant roles such as Design Verification Engineer at Marvell Semiconductor, where work involved machine learning SoC verification, and Technical Marketing Engineer at Cavium, specializing in data center switch products. Additional roles include positions at Cadence Design Systems, Micron Technology, Broadcom, Xilinx, and Cisco Systems, with expertise in ASIC verification, hardware design, and test bench architecture using SystemVerilog. Paresh Upadhyay holds a Master of Science in Computer Science from Georgia Institute of Technology, an MS in Electrical Engineering from the University of South Florida, and a Bachelor's degree in Electrical Engineering from L D College of Engineering, Ahmedabad.