Vivek Singh Parihar

Vivek Singh Parihar is a seasoned software professional with over 9 years of experience in embedded software system projects focused on automotive and avionics electronics. Currently serving as a Senior Technical Leader at KPIT since December 2014, Vivek possesses a robust background in hardware-software integration testing, unit testing, and model-based design using MATLAB. Previous roles include Technical Lead and Senior Software Engineer at KPIT, Software Engineer at HCL Technologies, and Software Engineer at Cyient, emphasizing verification and validation in embedded systems. Vivek holds a Bachelor of Engineering in Computer Science from Barkatullah University Institute of Technology Bhopal, completed in 2010.