Tzon-Tzer Lu

Tzon-Tzer Lu is an experienced engineering manager currently at NVIDIA since June 2018, specializing in chip level mixed signal design verification. Prior to this role, Tzon-Tzer worked as a Senior Analog Design Engineer at MediaTek, focusing on CMOS analog circuit design and PLL design for Serdes/BT Modem clock sources from March 2015 to June 2018. Earlier experience includes positions as an Engineer at Qualcomm, working on RF/Analog Circuit Design from December 2013 to February 2015, and at Hisilicon, specializing in Serdes Circuit design from July 2012 to December 2013. Tzon-Tzer holds a Master of Science and a Bachelor of Science in Electrical and Electronics Engineering from National Taiwan University, obtained between 2005 and 2011.