Sarvendu Sinha

Sarvendu Sinha is a Lead SoC DFT Engineer at Synopsys Inc since February 2023, with a solid background in Design for Test (DFT) across multiple prestigious companies. Prior to Synopsys, Sarvendu served as a DFT Design Engineer at Intel Corporation from February 2021 to January 2023, where responsibilities included ATPG pattern generation and leading a team for SoC ATPG and GLS activities. As a Senior DFT Engineer at Analog Devices from October 2019 to February 2021, Sarvendu managed memory repair flow setups and automated test conversions. Experience also includes a Technical Lead role at STMicroelectronics, overseeing ATPG simulation and methodology development, and as an Automotive DFT Design Engineer at NXP (formerly Freescale Semiconductor), focusing on MBIST integration and design debugging. Sarvendu holds a B. Tech in Electronics and Communication Engineering from Motilal Nehru National Institute Of Technology, earned in 2014.