Swarup Pattanayak

Swarup Pattanayak is a Principal Engineer at Synopsys India Pvt Ltd since May 2017, specializing in low power implementation using Unified Power Format (UPF) for FPGA-based emulation and prototyping. Prior to this, Swarup held the position of Sr. Staff R&D Engineer at the same company from May 2004 to February 2017, focusing on integrating UPF support within the VCS simulator, enhancing runtime and compile performance. Swarup’s earlier experience includes a role as a Sr. Software Engineer, optimizing VHDL compile performance, and as a Lead R&D Engineer at Interra Systems, working on a Verilog analyzer tool. Educational qualifications include a Post Graduate Program in Artificial Intelligence and Machine Learning from The University of Texas at Austin, a B.Tech in Computer Science & Engineering, and a Bachelor of Science in Physics from the University of Calcutta.