Jaydev Vn

Jaydev VN is a seasoned professional in the field of VLSI design and project management, currently serving as a Senior Manager at Aatral Technologies India Pvt Ltd since January 2023. With extensive experience at Capgemini as a Senior Manager in Semicon-VLSI since April 2018, Jaydev VN has developed expertise in technical project management, AMS, RF, library development, physical design, and verification. Previous roles include Technical Manager at Azventa Technologies, Lead Layout Designer at ARM, and Memory Layout Design Engineer at Intel Corporation, along with experience as an Analog Mixed Signal Layout Designer at Analog Devices and VLSI Layout Design Engineer at NetLogic Microsystems. Jaydev VN holds an MSc in Engineering in VLSI Design from Ramaiah Institute of Technology.