Harry Lee

Harry Lee has extensive experience in the field of semiconductor design and layout. Harry worked as a Sr. Mask Designer at Achronix Semiconductor Corporation starting in 2022. Prior to that, they worked at Synopsys Inc from 2018 to 2022, initially as a Layout Engineer, II, and later as a Layout Design Engineer, Sr I. During their time at Synopsys, they focused on complete OTP memory chip layouts in various technologies, including TSMC 5/6/7/12/16nm. Harry handled tasks such as floor planning and drawing core blocks using layout techniques for low noise, high speed, and precision matching.

Before joining Synopsys, Harry worked at Kilopass (now part of Synopsys) from 2015 to 2018 as a Layout Engineer. Here, they worked on a full OTP chip with TSMC 10/16/55nm and GF 22nm technologies, designing and building core test structures using the latest technology. Harry also gained experience in layout migration between foundries.

Furthermore, Harry's experience includes a brief stint at Tetratron Technology in 2015 as a Layout Designer, where they were involved in the layout of standard cells and analog blocks using SMIC 18um CMOS technology.

Overall, Harry Lee's work experience showcases their expertise in mask design, layout engineering, and working with various semiconductor technologies.

Harry Lee completed a Certificate of course completion in IC Mask Design at Silicon Drafting Institute in 2014. Prior to that, they earned a Bachelor of Arts degree in History from the University of California, Davis, where they studied from 2007 to 2011.