Naveen Bharathwaj Akesh

Naveen Bharathwaj Akesh has a diverse work experience in the field of semiconductor engineering. Naveen Bharathwaj started their career at the University of Michigan, where they worked as a Research Assistant. During this time, they were involved in projects related to configurable memory and conducted testing and evaluation of a Low Power Talking Book. Naveen Bharathwaj also developed driver interfaces for on-chip components.

In 2014, Naveen joined Oracle as a Senior Hardware Engineer. Here, they demonstrated their expertise in statistical analysis by developing a tool that reduced library LVF characterization time by 35%. Naveen Bharathwaj also implemented POCV methodology to apply process margins in STA and collaborated with the foundry to finalize POCV guard band for aging effects.

Since 2017, Naveen has been working at Achronix Semiconductor Corporation. Naveen Bharathwaj started as a Senior Hardware Engineer and later progressed to the roles of Staff Engineer and Senior Staff Engineer. Details of their work responsibilities during this period are not provided.

Overall, Naveen has gained significant experience in semiconductor engineering, with a focus on statistical analysis, layout design, testing, and performance evaluation.

Naveen Bharathwaj Akesh obtained their Bachelor's Degree in Electrical, Electronics and Communications Engineering from Anna University. Naveen Bharathwaj completed this degree from 2008 to 2012. Following this, they pursued a Master's Degree in VLSI from the University of Michigan, from 2012 to 2014.