Jagan Jeyaraj

Jagan Jeyaraj is a seasoned engineering professional with extensive experience in SoC design and ASIC prototyping. Currently serving as a Sr. Staff SoC Design Engineer at Aeva since May 2023, Jagan previously held the role of IP Logic Design Engineer at Intel Corporation from December 2016 to May 2023, focusing on RTL design. Prior to that, Jagan worked as a Technical Consultant at Wipro from August 2008 to December 2016, engaging in ASIC prototyping, RTL integration, and IP validation. Earlier career roles include Technical Specialist at Infosys, Software Design Engineer at Visteon, and Software Engineer at Larsen & Toubro, with experience spanning domains such as medical electronics and automotive infotainment. Jagan holds a Bachelor of Technology in Electronics from the Madras Institute of Technology, earned between 1999 and 2003.