Khachatur Armenyan

Khachatur Armenyan is an experienced ASIC Design Engineer with a robust background in semiconductor design and development. Currently employed at Aeva since July 2021, Khachatur previously held positions at Intel Corporation as a SoC Design Engineer and at Synopsys Inc as a Senior Staff Applications Engineer. Notable achievements include creating an architecture for a digital signature algorithm hardware accelerator at Intel and delivering complex BIST IP integration solutions at Synopsys. Prior roles involved managing a team of engineers in CAE at Virage Logic, focusing on DFT and post-sales support. Khachatur began their career as an RTL Design Engineer at Hylink, working on crypto ASIC projects, and holds an Ms degree in Radioelectronics and Communication from the State Engineering University of Armenia.