S K.

Sharat Kandregula is a seasoned Hardware Engineer with expertise in System on Chip (SoC) design verification, currently employed at Aeva since May 2021. Previously, Sharat served as a Senior Engineer at Qualcomm from June 2017 to April 2021, specializing in object-oriented testbench development, low power verification, and various testing methodologies. Proficient in UVM, SystemVerilog, C, and Python, Sharat possesses strong capabilities in power-aware RTL design, digital filter design, gate-level debugging, and silicon test and characterization. Sharat holds a Master of Technology in Communication Networks and a Bachelor of Technology in Electrical, Electronics and Communications Engineering, both from the National Institute of Technology Rourkela.