Harieswar Meenuga

Harieswar Meenuga is an ASIC Design Engineer at Alphawave IP Group since September 2022, following experience as a Physical Design Intern at OpenFive from April 2022 to September 2022. Harieswar completed a Bachelor of Technology in Electrical, Electronics and Communications Engineering at Sri Venkateswara University from August 2019 to April 2022 and also earned a High School Diploma in the same field at Sri Venkateswara University College of Engineering between 2020 and 2022.