Jared Cheng

Jared Cheng is a Full Cycle FPGA Engineer at Applied Signal Technology since August 2023. Previously, Jared gained experience as an FPGA Intern at Raytheon Intelligence & Space, focusing on IP Verification of Flash Memory Controller and firmware support for next-generation projects. As an Undergraduate Research Assistant at Martin Group, Jared conducted research on Thin-Film Mixed Ionic Electronic Conductors and Ferroelectric Devices, utilizing various analytical techniques such as X-Ray Diffraction and Piezoelectric Force Microscopy. Involvement in the CubeSat project at Space Technologies At California included using PCB Design software for electrical board assembly. Jared's internship at NASA Jet Propulsion Laboratory involved optimizing data processing for the Mars 2020 Rover Instrument Data Systems Pipeline, achieving significant cost reductions. Additionally, participation in the Materials Project at UC Berkeley involved developing algorithms for diffraction pattern analysis. Jared holds a Bachelor of Applied Science in Materials Science and Engineering/Electrical Engineering and Computer Science from the University of California, Berkeley.