Eric Howard

Eric Howard has extensive work experience in the technology industry. Eric started their career at Intel Corporation as a Member of the Technical Staff from June 1990 to February 1992. Eric then joined High Level Design Systems as a Principal Software Architect from February 1992 to February 1997. Following that, they worked at Cadence Design Systems as a Senior Manager of Engineering from March 1997 to March 1999.

Eric then moved to InTime Software where they served as a Software Architect from April 1999 to January 2004. During this time, they played a key role in developing RTL timing methodology and design flow. Eric also drove correlation between RTL and gate level timing.

Afterward, Eric joined Silicon Navigator as a Senior Software Architect from January 2004 to January 2008. Here, they developed a C++ API for a standalone static timing engine and integrated the Concept schematic system onto Open Access (OA).

Next, they joined Chip Path Design Systems as an Architect from January 2008 to September 2014. In this role, they architected and developed a physical-design based static timing analysis tool. Eric also implemented features like RTL processing, timing, placement, and power calculations.

Most recently, Eric worked at Arteris as a Senior Software Engineer starting in September 2014. Their responsibilities included implementing a streamlined SDC constraint generator for a cache coherent network on chip design tool and creating a regression environment for code coverage and regression tests.

Throughout their career, Eric has demonstrated expertise in software architecture, design flow, static timing analysis, and RTL timing methodology.

Eric Howard obtained a Bachelor of Engineering (B.E.) degree in Electrical Engineering and Computer Science from the University of California, Berkeley in the years 1985 to 1990.