Matija Miletic

Matija Miletic is a Senior Verification Engineer at CEVA, Inc. since March 2022, with prior experience as a Senior Design Verification Engineer at NoBug Consulting, focusing on projects for Intel from November 2016 to March 2022. In this role, Matija Miletic handled IP verification for Ethernet PHY, including JTAG and Test Access Port verification, and developed LIN protocol verification environments. Earlier experience includes working as a Verification Engineer for Texas Instruments Germany at ELSYS Eastern Europe, where Matija Miletic contributed to SoC verification and development of test cases for various components. Matija Miletic holds a Master's degree in Electronics from the School of Electrical Engineering, University of Belgrade, completed between 2014 and 2016, and a Bachelor's degree in the same field from 2010 to 2014.