Paulo Morais

Paulo Morais is an experienced IC Layout Engineer with a strong background in designing analog and mixed-signal CMOS circuits across various technology nodes, including 0.35 µm to 65 nm. Current role at CML Microcircuits commenced in August 2012. Prior positions include IC Layout Contractor at imec and multiple contracting roles at DNAE, eoSemi Ltd, and Synopsys, with notable contributions to the Analog Design Group's internal PLL in Gdansk, Poland. A tenure as Senior Layout Designer at Silicon Laboratories involved work within the Broadcast Division, while foundational experience was gained at MIPS Technologies and Chipidea, where Paulo participated in approximately 50 projects focused on ADC Pipeline, AFE, DAC, SAR, and RF designs. Education was completed at AFTEM/ESTEM from 2000 to 2002.