Ajith Bala B

Ajith Bala B is a Design Engineer at CoreEL Technologies since August 2023. Ajith's prior experience includes participation as a member in the IEEE SASTRA student branch from August 2021 to July 2023 and serving as Team Lead for the Deneb Cluster in IEEE Region 10 Young Professional - CLAP 2021. Ajith completed a Bachelor of Technology in Electrical, Electronics and Communications Engineering from Shanmugha Arts, Science, Technology & Research Academy (SASTRA) from 2019 to 2023. Internship experience includes working as an FPGA Design Intern at Society For Electronic Transactions and Security (SETS) from January 2023 to May 2023, focusing on garbled AES design and hardware implementation against side channel attacks, and as an Embedded Engineer Intern at RKN Designs and Solutions from February 2022 to November 2022 on a project approved by Nidhi Prayas. Prior education includes completing Higher Secondary studies at Chinmaya Vidyalaya from 2004 to 2019.