Veera Manikanta Chenna

Veera Manikanta Chenna is a Senior Design Engineer at CoreEL Technologies since January 2021, specializing in RADAR project development and testing, utilizing baremetal and Petalinux environments on Xilinx FPGA. Previously, Veera held the position of Design Engineer, contributing to various defense and communication projects involving the development and testing of interfaces such as UART, IIC, SPI, Ethernet, Flash, DDR, ADC, and DAC. Veera gained foundational experience through embedded systems training from July 2019 to January 2020 and an internship at Bharat Sanchar Nigam Limited in May 2018. Veera holds a Bachelor of Technology degree in Electronics and Communications Engineering from Godavari Institute of Engineering & Technology, completed in 2019.