Mounica R.

Mounica R. is a Senior Engineer III specializing in Analog Mixed Signal at Cyient since April 2022. Prior experience includes a role as Senior Engineer - Custom Layout Engineer at HCL Technologies from February 2021 to March 2022, and Analog Layout Engineer positions at RiseTime Semiconductors and Kalatronics Consultancy Services Pvt Ltd. Mounica began the engineering career as an Analog Layout Trainee Engineer at SumedhaIT in early 2018. Educational qualifications include an M.Tech in VLSI System Design from CVR College of Engineering, Hyderabad (2015-2017), and a Bachelor of Technology in Electronics and Communications Engineering from Vignan Institute of Technology and Science (2011-2015).