Senthil Duraisamy

Senthil Duraisamy has over 17 years of experience in the semiconductor industry. In 2004, they began their career at Wipro as a Project Engineer, where they were responsible for the development of test environment and cases for the Multi Band OFDM Alliance MAC H/W Subsystem. In 2005, they joined SiRF Technology (from TrueSpan Acquisition) as an ASIC Design Engineer, where they helped develop Mobile TV Receiver Chipset from concept in paper to first-time silicon success with working customer samples. From 2008 to 2014, they worked at SmartPlay Technologies (from Techforce acquisition) as a Senior Technical Lead / Reporting Manager, consulting for Cypress Semiconductors, Qualcomm, Xilinx, and Aura Semiconductors. Senthil then joined Qualcomm (from CSR acquisition) as a Staff Engineer, where they worked in Processor, SV/OVM. In 2015, they joined Juniper Networks as an ASIC Engineer, Senior Staff, leading the successful execution of the latest express fabric ASIC with first time silicon success. Currently, they are a Senior Principal Engineer at d-Matrix, where they are part of a highly talented team in the process of setting up office in India and is learning new domain- AI / ML. Senthil is pushing the inferencing compute boundary by introducing DIMC using chiplet architecture.

Senthil Duraisamy has a Bachelor of Engineering (Honors) in Electrical & Electronics from Birla Institute of Technology and Science, Pilani from 2000 to 2004. Senthil then pursued a Post Graduate Diploma in Business Administration from All India Institue of Management Studies, Chennai from 2006 to 2007.