Alexandre Réauté de Nadaillac

Alexandre Réauté de Nadaillac has a diverse work experience, starting with their current position as an ASIC engineer at Elsys Design since August 2020. Previously, they were a FPGA engineer at Elsys Design from June to August 2020, and from April to September 2019. In these roles, they developed functional generic blocks for low-level image processing, wrote concept and design documents, coded RTL designs, and verified IPs. Alexandre also conducted synthesis, placement, and routing on Zynq Ultrascale+ targets. Throughout their work at Elsys Design, they improved their skills in Systemverilog, Verilog, Xilinx Vivado, Synplify, Git, and QuestaSim.

Before their time at Elsys Design, Alexandre had an internship at TACHYSSEMA DEVELOPPEMENT from March to September 2018. Alexandre also had a student internship at Université d'Ottawa in February and March 2017.

In addition, Alexandre has prior experience as a service technician at Saint-Gobain in July and August 2016. Alexandre also worked summer jobs at Monoprix in July and August 2011, and in July 2010.

Overall, Alexandre Réauté de Nadaillac has gained significant experience in the fields of ASIC and FPGA engineering, while also contributing to various other roles and industries.

Alexandre Réauté de Nadaillac's education history begins in 2012 when they obtained their French equivalent of a High School diploma with distinctions, also known as the Baccalauréat avec mention Bien. From 2012 to 2015, they attended the Lycee Marcelin Berthelot where they studied Mathematics, Physics, and Chemistry. In 2015, they enrolled at ENSEEIHT and pursued a degree in Electronique et Traitement du Signal (Electronic and Signal Processing), which they completed in 2018. In 2017, they also had a brief stint at Technische Universität Berlin, where they focused on Electronic studies.