Gopishankar Thayyil

Gopishankar Thayyil is a Digital Design and Verification Engineer at ESS Technology, Inc. since June 2023, specializing in RTL Design & Verification, Digital Place & Route, Formal Verification, DFT Scan Tests & BIST, and ECO. Previously, Gopishankar engaged in a graduate research project on the parallel ultra-low power (PULP) platform LLC at the University of Waterloo from December 2022 to May 2023 under Prof. Rodolfo Pellizzoni. Prior experience includes serving as an ASIC Design and Verification Trainee at Indicus Technology, where Gopishankar focused on Verilog HDL design and implementation, static timing analysis, and functional coverage using System Verilog. Gopishankar holds a Master of Engineering in Electrical and Computer Engineering from the University of Waterloo and a Bachelor of Engineering in Electronics and Communications Engineering from Vishwakarma Government Engineering College. Early education was completed at Rachana School in India.