Gaurav Hatwalne

Gaurav Hatwalne is a seasoned engineer with a strong background in analog design and verification. Currently serving as a Senior Engineer at NXP Semiconductors since April 2024, Gaurav focuses on design and performance improvements for POR IP using UMC 28nm process technology. Gaurav also holds the position of Lead Engineer Analog Design at Eteros Technologies and previously worked at Tessolve from October 2018 to December 2023, contributing to various IPs, including Sigma-Delta Modulators and an advanced 10-bit SAR ADC. Gaurav's experience includes a role as a Circuit Design Engineer at Intel Corporation from June 2019 to November 2022. Gaurav completed a degree in engineering from Yeshwantrao Chavhan College of Engineering, Nagpur in 2017.