Rahul Vyas

Rahul Vyas is a skilled SoC Engineer at Fortaegis Technologies, specializing in System on Chip design for ultra-secure semiconductors since March 2024. Prior experience includes a role as Digital Design Engineer at Qblox, where Rahul designed low latency systems for controlling quantum computers. At Hyperion Technologies B.V., significant contributions were made to FPGA-based satellite systems, including high-speed MODEM designs and memory management systems. Rahul also engaged in mentoring and development during Google Summer of Code, focusing on FPGA-based video processing, and completed internships at CERN and WESEE, contributing to advanced projects in technology and avionics. Educational qualifications include a Master of Science in Computer Engineering from Delft University of Technology and a Bachelor of Technology in Electronics and Communications Engineering from The LNM Institute of Information Technology.