Arun Kumar S

Arun Kumar S is a Senior Engineer at Infinera since November 2013, with prior experience as an R&D Engineer at Tejas Networks Ltd. from July 2010 to November 2013. Arun has expertise in FPGA-based designs, notably developing a memory-efficient 128-point pipelined FFT processor for MB-OFDM UWB systems and achieving significant performance milestones on ALTERA Stratix III. Additionally, Arun has contributed to X86 core design using Bluespec System Verilog. Educationally, Arun holds a BTech in Electronics and Communication from the National Institute of Technology, Tiruchirappalli, completed in 2010, and attended Kendriya Vidyalaya from 1993 to 2005.