Michael Yeo

Michael Yeo has extensive experience in semiconductor and ASIC engineering, currently serving as the Senior Director of ASIC Engineering at Jariet Technologies, Inc. since February 2016, overseeing the digital frontend group and managing ASIC and IP projects. Previous roles include Director of VLSI at ClariPhy Communications, where responsibilities included managing digital ASIC projects, and Director of ASIC Engineering at FutureWei Technologies, focusing on wireless baseband processing ASIC. Earlier career highlights include serving as an Electrical Engineer at LJ Gonzer with contributions to the Windsor Blue supercomputer and managing multiple IC development projects as a Senior Manager at Transwitch Corp. Michael Yeo holds a Master's and Bachelor's degree in Computer Engineering from the University of Bridgeport.