Cheng Hung Hsieh

Cheng Hung Hsieh has worked in the design verification field since 2015. From 2015-2019, they worked as a Digital Design Engineer at \u7fa4\u806f\u96fb\u5b50\u80a1\u4efd\u6709\u9650\u516c\u53f8, where they built simulation, regression, coverage and several auto-gen perl scripts for verification. Cheng Hung also built SV simulation environments for FIP (Flash IP controller) using their direct pattern code-gen methodology and self-check checker methodology. Since 2019, they have worked as a Senior Staff Engineer (Design Verification) at Kneron, where they have improved simulation, regression, coverage and built several auto-gen python scripts for verification. Cheng Hung has also built sub module UVM simulation environments for NPU (Neural Processor Unit) and maintained the rest of the sub modules from other two resigned staffs. Cheng Hung has also built sub and top module UVM simulation environments for IE (Image Processor Engine) using UVMC lib, Synopsys AXI VIP.

Cheng Hung Hsieh attended National Cheng Kung University from 2007 to 2011, where they earned a Bachelor's degree in Electrical Engineering. Cheng Hung then returned to the same university from 2011 to 2014, obtaining a Master's degree in the same field.