Brian Jia

Brian (Hong) Jia is an experienced engineering professional with a robust background in VLSI design and physical design management. Currently serving as Manager II of Mask Design at Lattice Semiconductor since August 2002, Brian oversees all physical design aspects, manages schedules, and leads an ASIC team in tape-outs for CPLD and FPGA projects. Previously, at Cerdelinx Technologies, Brian held the position of Manager of VLSI Design, focusing on ASIC flow and verification for high-speed communication ICs while developing CAD flows. With prior experience at Broadcom Corporation and Trident Microsystems, where Brian contributed to ASIC flow studies and the successful tape-out of over 20 advanced graphic chips, Brian possesses extensive expertise in tools such as Synopsys, Verilog, and Hspice. Brian holds a Master’s degree in Engineering Science from Clarkson University and a Bachelor’s degree in Physics from Tsinghua University in Beijing.