Baburaj Thillaigovindan

Baburaj Thillaigovindan is a seasoned manager in ASIC design with extensive experience in the semiconductor industry. Currently serving as the Manager of ASIC Design at MaxLinear since March 2022, Baburaj oversees advanced multi-core LTE silicon integration and facilitates FPGA prototyping and emulation. Prior roles include Manager of ASIC Design and Manager of Silicon Validation at MBIT Wireless Private Limited, where responsibilities encompassed LTE SoC functional validation, PMIC validation, and developing automation systems using NI LabVIEW and TestStand. Previous experience includes nearly 11 years at Microchip Technology as a Principal Engineer focused on Verilog RTL coding and chip validation, as well as a Project Associate role at the College of Engineering, Guindy, where contributions were made to the ANUSAT project. Baburaj holds a Master’s degree in VLSI (Microelectronics) from the College of Engineering, Guindy, and a Bachelor’s degree in Electrical and Electronics Engineering from Karunya Institute of Technology and Sciences.