Frederic Sievert

Frederic Sievert has extensive work experience in the field of electrical design engineering, specializing in RTL2GDS and physical design. Frederic started their career at Dolphin as a Microelectronics Engineer from 2002 to 2005. Frederic then worked at Artware as an Engineer in 2005. From 2006 to 2012, they joined Texas Instrument as an Electrical Design Engineer, where they developed power and area estimation tools for low-power methodologies in 28nm and 45nm technologies. In 2012, they worked at ST-Ericsson as an RTL2GDS Engineer before joining Intel Corporation in 2013 as an RTL2GDS Senior Engineer, where they worked until 2020. Currently, they are employed at MaxLinear as a Principal Physical Design Engineer, leading the synthesis, STA, and timing closure for Wi-Fi chipsets in the 16nm node. Frederic also collaborates with cross-functional teams to ensure successful integration and timing convergence.

Frederic Sievert began their education at Université Louis Pasteur (Strasbourg I) from 1997 to 1999, where they earned a Bachelor's degree in IUT Mesures Physiques. Frederic then attended Université Henri Poincaré, Nancy 1, from 1999 to 2001, completing a Bachelor's/Master's program in IUP GEII. Frederic continued their education at the same institution from 2001 to 2002, obtaining a Master's degree in DESS ISEE. These are the known educational milestones in Frederic Sievert's history.