Jayadev Devagiri

Jayadev Devagiri has a diverse work experience in the field of digital design engineering. Jayadev currently works at MemryX Inc. as a Digital Design Engineer. Prior to this, they worked at Intel Corporation from 2018 to 2023, where they were involved in RTL development, LINT, CDC, and UPF delivery for the Foveros Die to Die interconnect and the GPIO subsystem RTL development of Discrete graphics SOCs. Jayadev also worked on PCIE Subsystem RTL integration to the SOC. Before Intel, they worked at Cypress Semiconductor Corporation as a Sr Elect Design Engr from 2016 to 2018. Jayadev gained experience in standard 802.11 protocols, wireless MAC low power design, PALLADIUM quickturn emulation, and WiFi chip DV team at Broadcom from 2015 to 2016. Jayadev started their career as an Intern Design Engineer at Vitesse Semiconductor, now Microsemi, in 2015. In 2014, they interned at RCI DRDO.

Jayadev Devagiri completed their education in a chronological order. From 2009 to 2013, they attended Ramaiah Institute Of Technology, where they received a Bachelor's degree (B.E) in Electronics and Communication. Following this, from 2013 to 2015, they pursued a Master of Technology (M.Tech.) at the International Institute of Information Technology Hyderabad (IIITH), specializing in VLSI and CE. In September 2014, Jayadev also obtained a certification as an AMCAT Certified Data Processing Specialist from Aspiring Minds.