Harshini Yerra

Harshini Yerra currently serves as the Functional Safety Design Lead at Microchip Technology Inc., a position held since September 2023. Prior experience spans over thirteen years at Intel Corporation in various roles, including Performance & Competitive Architecture Analysis and Platform Architect, among others. Additionally, Harshini has held leadership positions such as Chair of the IEEE ASU Student Chapter and Secretary of IEEE ASU. Early career experiences include internships at Intel, Texas Instruments, and CMC Ltd, with responsibilities in validation and verification processes in engineering contexts. Educational qualifications include an MSE in Analog & Mixed Signal Circuit Design from Arizona State University and a B.E. in Electrical, Electronics & Communications Engineering along with an M.Sc. in Physics from Birla Institute of Technology and Science, Pilani.