Sebastian Copacian

Sebastian Copacian has a diverse range of work experience in the field of engineering. Sebastian began their career at Microchip Technology in 2011, where they worked as a Digital Design and Verification Engineer. During their time there, they were responsible for verifying various PIC Microcontroller families and designing the receiver part for a module with DALI, DMX, LIN, and UART protocols. Sebastian utilized skills such as Assembly, Verilog, and SystemVerilog.

In 2016, Sebastian joined TTTech Computertechnik AG as a Verification Engineer for ASICs & FPGAs. In this role, they were part of the verification team for Time Triggered Technology Switches, focusing on best effort and critical traffic. Sebastian gained experience in SystemVerilog UVM, VHDL, Python, and C.

In 2019, Sebastian moved to EASYIC DESIGN as a Verification Engineer, working as a subcontractor for Intel Dublin. Sebastian was a member of the NoC verification team and utilised skills such as SystemVerilog UVM, Python, and AMBA protocols.

Afterwards, Sebastian joined ams AG in 2019 as a Verification Engineer. Sebastian was responsible for SoC verification using the UVM methodology, with expertise in SystemVerilog UVM.

Their most recent role is at NeuroBlade, where they currently work as a Functional Verification Engineer, starting in 2020. Additional information, such as the end dates for this role and their roles at ams AG and EASYIC DESIGN, is unavailable.

Sebastian Copacian pursued a Bachelor's Degree in Electrical, Electronics, and Communications Engineering from the Technical University of Cluj Napoca between 2006 and 2010. Sebastian then went on to obtain a Master's Degree in Digital Signal Processing in Telecommunication Systems from the University POLITEHNICA of Bucharest from 2010 to 2012.