Pravin Shah

Pravin Shah has over 35 years of work experience in the field of engineering. Pravin began their career in 1985 as a Member of Technical Staff at SGI. In 1995, they joined Cisco Systems as a Senior ASIC Design Engineer. Pravin then moved to Nokia Networks (via Amber Networks acquisition) in 1999 as a Senior Manager of ASIC Development, where they were responsible for managing and leading the development of complex Xilinx FPGAs and a Network Processor ASIC. In 2005, they became the Director of Hardware FPGA Systems at Matisse Networks, where they managed and led the development of 6 complex Xilinx FPGAs. Pravin then moved to Vello Systems in 2011 as a Senior Staff Project Manager, where they were responsible for bringing SDN data path switches and SDN controller servers into conformity with company branding and agency certifications. In 2013, they joined AOptix Technologies as a Senior Staff Design and Project Manager, where they designed and managed development of chips and HW for Ethernet Wireless Communication Technology. Pravin then moved to Altera in 2014 as a Senior Design Manager, where they led multiple generations of FPGA Silicon chip releases. Finally, in 2018, they joined NovuMind Inc. as Director of ASIC Development, where they managed Silicon Design and Technical Program Management of next generation Convolution Neural Networks accelerator AI chips. Pravin is currently employed at Marvell Technology as a Principal Engineering Project Manager.

Pravin Shah graduated from the Indian Institute of Technology, Kharagpur with a BTech in Electronics & Electrical Communications Enginerring. Pravin then furthered their education at Oregon State University, where they obtained an MSEE in Computer Engineering.