Tarachand Pagarani

Tarachand Pagarani has over 10 years of experience in the semiconductor industry. Tarachand started their career in 2005 at Quicklogic as an EDA Tools Manager. In 2008, they joined Synopsys as an R&D Manager, where they managed the IC compiler (ICC) Clock Tree Synthesis & Clock-Mesh Technology R&D team. Tarachand worked on overall ICC CTS product development and management, supporting critical customer tape-outs. Tarachand returned to QuickLogic in 2011 in the role of Director of Software. Tarachand then took on the role of Country Manager/Sr. Director of Software in 2016. Currently, Tarachand is serving as the Director of Engineering at QuickLogic Corporation.

Tarachand Pagarani attended Devi Ahilya Vishwavidyalaya from 1993 to 1997 with an unspecified degree and field of study. Tarachand then pursued a Master of Science degree in Computer Engineering at Case Western Reserve University from 1997 to 1999.