Chin Li Lo

Chin Li Lo has extensive work experience in the field of engineering, focusing on semiconductor and technology design. Chin Li is currently employed as a Senior Principal Design Engineer at Rambus. Prior to that, they worked as an Engineer at PLDA from October 2019 to August 2021. Chin Li also served as a Technical Manager at 创意电子 from July 2018 to October 2019. Additionally, they worked at Huawei as a Senior Engineer from April 2012 to June 2018, where they were responsible for DDRPHY digital part design, PCIE transaction layer design, and Unipro L2 preemption design. Before that, they held the role of Chief Engineer at 凌通科技 Generalplus from January 2009 to April 2012, where they focused on TV game related IC support and Sony DPF IC support. From July 2005 to December 2008, they worked as a Senior Engineer at 凌陽科技, specializing in TV game and ELA chip design, PPU IP design, and SD card/Nand Flash controller design. Chin Li began their career at Silicon Integrated Systems as a Senior Engineer from October 2001 to June 2005.

Chin Li Lo completed a Master of Science (MS) in Computer Science from National Chung Cheng University from 1999 to 2001. Prior to that, they obtained a Bachelor of Science (BS) in Computer Science and Information Engineering from National Chiao Tung University from 1995 to 1999.