Jorge Padilla

Jorge Padilla is an experienced Photonics Layout Engineer with a strong background in designing and delivering GDSII files for silicon photonic devices. Current work at Rockley Photonics Inc. involves providing design rule documentation for various teams. Prior work experience includes positions at Mellanox Technologies and Juniper Networks, where responsibilities encompassed creating layouts for a range of photonic devices, automating wafer level mapping, and maintaining layer definitions. Jorge Padilla holds a Master of Science degree in Electronics & Photonics and a certificate in Management Practice from UC Santa Barbara, along with a Bachelor of Science degree in Electrical Engineering from the same institution.