Arathi J.

Arathi J. is a Senior Design Verification Engineer at SeviTech Systems Pvt. Ltd. since December 2021, previously holding the position of Engineer I at INVECAS from January 2019 to August 2021, where responsibilities included System on Chip (SoC) level verification of Display Port protocol for transmitter side designs. Arathi also contributed to SoC level verification using Mentor Receiver VIP and conducted loop-back tests connecting transmitter and receiver devices. Prior experience includes a Design Verification Internship at MACOM from March 2018 to November 2018 and training at Mentor Graphics in June 2016, focusing on verification using System Verilog. Academic qualifications include a Master’s degree in VLSI and Embedded Systems from SGGS College, Nanded, and a Bachelor of Engineering in Electronics Engineering from D.K.T.E Institute, Shivaji University.