Manikanta Kopparapu

Manikanta Kopparapu is a Senior Engineer at Silicon Labs, with experience starting from November 2019 and focusing on the Power Simulations environment bring-up. Prior to this role, Manikanta worked as an Engineer developing UVM test bench components for the I3C protocol and integrating these components with the design under test. From November 2017 to November 2019, Manikanta served as a SOC Verification Engineer at HCL Technologies, specializing in various protocols including SPI, GPIO, DMA, and QSPI, along with writing test cases for these protocols. Manikanta holds a Master’s Degree in VLSI Design from Vellore Institute of Technology and a B.Tech in Electronics and Communication Engineering from SVIST Engineering College. Educational background includes an Intermediate degree in M.P.C from Narayana Junior College and an S.S.C from Nagarjuna High School.