Jaya Praveen

JAYA Praveen is a senior physical design engineer with over 4 years of experience in VLSI physical design. Currently employed at SiSoC Semiconductor Technologies Pvt Ltd since July 2021, JAYA has expertise in block level implementations across various technology nodes including 5nm, 14nm, and 28nm. Previous experience at Diginet Systems from December 2017 to June 2021 includes roles as ASIC physical design engineer, focusing on the RTL-to-GDSII physical design flow, comprising synthesis, place and route (PNR), and sign-off checks. JAYA has demonstrated proficiency in resolving congestion and conducting timing quality checks in block level designs, with hands-on experience in 40nm, 28nm, 14nm, and 5nm process nodes. JAYA holds a Master of Technology in VLSI & ESD and a Bachelor of Technology from JNTU Anantapur.