Weilun Chang

Weilun Chang has extensive work experience in the field of VLSI engineering. Weilun started their career in 2003 as a Sr Logic Design Engineer at ITE, where they worked on designing JPEG decoding accelerators and MPEG2 hardware accelerators. Weilun also gained experience in FPGA synthesis, debugging, and hardware/software co-design. In 2006, they joined Qpixel Technology as a Sr. VLSI Engineer, where they focused on motion refinement design for MPEG4 AVC (H. 264) and developed algorithms for motion vector prediction. In 2011, they joined Sigma Designs as a Staff ASIC Engineer, responsible for all aspects of logic design for MPEG4 AVC motion refinement design, including micro-architecture, pipelining, low-power design, timing closure, and chip bring-up. Since 2013, they have been working as a Principal Engineer at SK hynix memory solutions inc. providing their expertise in VLSI engineering.

Weilun Chang completed a Bachelor of Science (B.S.) degree in Nuclear Engineering from National Tsing Hua University, where they studied from 1990 to 1994. Weilun further pursued their education at the University of Massachusetts Amherst, where they obtained a Master of Science (MS) degree in Electrical and Computer Engineering from 1997 to 1999.