Yi Rao

Yi Rao has a diverse work experience in various companies. They started working as a VLSI Design Engineer at the National VLSI Design Center in 2004 and stayed there until 2006. They then moved to Synopsys, where they worked as a Design Verification Engineer for a year. Their responsibilities included developing and deploying IC design tools, troubleshooting design flow issues, and working on ICC timing analysis solutions.

In 2009, Yi Rao joined Marvell Semiconductor as a Senior Design Engineer and worked there for seven years. During this time, they gained expertise in design engineering. In 2011, they also started working at Intel Corporation as a Design Engineer, focusing on RTL design and low power implementation.

Their latest role is as a Staff Design Engineer at SK hynix memory solutions inc. since 2016. Their responsibilities include working on SSD SoC backend design, with tasks such as low power UPF, DC synthesis, timing constraints, conformal/LEC, ECO, and Primrtime timing analysis.

Overall, Yi Rao has accumulated significant experience in design engineering and has worked in companies like Marvell Semiconductor, Intel Corporation, Synopsys, and SK hynix memory solutions inc.

Yi Rao completed a Bachelor of Science degree in Electrical Engineering from ZHEJIANG UNIVERSITY, College of Engineering, from the year 2000 to 2004. Later, from the year 2007 to 2009, Yi Rao pursued a Master of Science degree in Electrical Engineering from Syracuse University.