Jayasri Veeravilli

Jayasri Veeravilli is a dedicated Physical Design Engineer I at SmartSoC Solutions Pvt Ltd, with experience starting from July 2022. Prior to this role, Jayasri held positions as a Physical Design Engineer Trainee and Project Engineer at Wipro from November 2021 to June 2022. Earlier experience includes a Program Analyst Trainee role at Cognizant from March 2021 to November 2021, a Research Intern position at VLSI System Design in May 2020, and a Summer Intern role at Electronics Corporation of India Limited (ECIL) in 2019. Jayasri earned a B.Tech in Electronics and Communication Engineering from SRM University, AP, graduating in May 2021.