Ran Harpaz

Ran Harpaz has extensive work experience in verification engineering, with a focus on developing testbenches and automating checkers flow. From 2023 onwards, they worked at Speedata.io as a Senior Verification Engineer, taking on the role of block and cluster owner and developing a UVM TB from scratch. Prior to this, they worked at AST SpaceMobile from 2021 to 2023, also as a Senior Verification Engineer. At Samsung Israel R&D Center - SIRC, where they worked from 2007 to 2021, they served as a Senior Verification Engineer and was responsible for writing test plans and developing SVTB and UVM testbenches. Ran also automated checkers flow using CSV format for designers' convenience. Ran Harpaz worked at LSI, an Avago Technologies Company, from 2005 to 2007 as a Verification Engineer, where they developed Specman and vManager environments using the eRM methodology. Their earliest work experience in verification engineering was at Marvell Semiconductor from 2001 to 2004, where they held the role of Verification Engineer.

Ran Harpaz completed a Bachelor of Technology in Electrical & Electronic Engineering from Ariel University, specializing in the field of Electrical & Electronic Engineering. Ran attended the university from 1997 to 2000.